// -*- Verilog -*-
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

//    lib.map file:
include ./t_config_libmap_inc.map

library rtllib *.v;
library rtllib2 *.v, *.sv;
library rtllib3 *.v -incdir *.vh;
library rtllib4 *.v -incdir *.vh, *.svh;

// Note this does not start a comment
library gatelib ./*.vg;
// */

config cfg;
   design t;
endconfig
